1. Field of the Invention
The present invention relates to a memory device and a method of fabricating the same. More particularly, the present invention relates to a memory device including a carbon nanotube that serves as a charge moving channel and a method of fabricating the memory device.
2. Description of the Related Art
Semiconductor memory devices fundamentally include a capacitor that preserves stored charges and a transistor that serves as a switch for securing a path of current necessary to write data to or read data from the capacitor.
To allow a high current to flow in a transistor, the transistor must have a high transconductance (gm). Hence, metal oxide field effect transistors (MOSFETs) having a high transconductance have been commonly used as switching devices of semiconductor memory devices.
MOSFETs basically include gate electrodes made of doped polycrystalline silicon and source and drain electrodes made of doped crystalline silicon.
The transconductance of MOSFETs is inversely proportional to the length (L) of a channel and the thickness of a gate oxide film, and is directly proportional to surface mobility, permittivity of the gate oxide film, and the width (W) of the channel. Since the surface mobility and the permittivity of the gate oxide film are respectively predetermined by a directional silicon wafer and a silicon oxide film, a high transconductance may be obtained by increasing a W/L ratio of the channel or by thinning the gate oxide film.
However, manufacturing highly integrated memory devices requires reducing the physical size of MOSFETs, which in turn requires reducing the physical sizes of gate, source, and drain electrodes, which leads to a variety of problems. When the size of a gate electrode in a transistor is reduced, the cross sectional area of the gate electrode is proportionately reduced. Such a reduction in the cross sectional area of a gate electrode leads to the formation of a high electrical resistance in the transistor. Similarly, the size of source and drain electrodes are reduced by reducing the thicknesses, or junction depths, thereof, also leading to the creation of a larger electrical resistance.
When reducing the size of a MOSFET, a distance between a source and a drain may be decreased, generating a phenomenon known as “punch through,” in which the source and a depletion layer of the drain come into contact, making it impossible to adjust the current flow. In addition, such a reduction in the size of a memory device causes the width of a channel serving as a current path to be reduced to 70 nm or less, preventing a smooth flow of current. Increased electrical resistance, punch through, and decreased channel width in MOSFETs result in heat loss, increased power consumption, electrical characteristic variations, charge leakage, etc., ultimately causing unacceptable memory device function.
Therefore, reducing the size of MOSFETs to create highly integrated semiconductor memory devices is limited by the inherent physical characteristics of MOSFETs. As a result, general memory devices based on MOSFETs are not suitable for use as future high-density memory devices, and an alternative is needed.